The switching characteristics of a trench-type 4H-SiC insulated-gate bipolar transistor (IGBT) device with interface defects are analyzed up to the nonquasi-static (NQS) switching regime using reported interface density measurements and device simulation. Collector current degradation characterized by threshold voltage shift to higher gate voltages and reduction of current magnitude due to carrier trapping are observed under quasi-static (QS) simulation condition. At slow switching of the gate voltage, carrier trapping causes a hump in the transient current at the start of conduction. At very fast switching, the current hump is limited by the NQS effect which results to a reduced switching efficiency and increased on-resistance.

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The dynamic characteristics of a 4H-SiC insulated-gate bipolar transistor (IGBT) at pulse switching is investigated by incorporating reported measurements of the interface defect density to device simulation. Different trap features such as energy states and trap time constants are investigated to determine the influence of traps on circuit performance. The capture cross-section parameter used in the simulation depicts the probability of traps to trap/detrap carriers which relates to the carrier trap time constant. It is demonstrated that trapped carriers from the on-state condition cause enhanced generation current during the off-state condition, which give rise to undesired leakage current in addition to the threshold voltage shift previously reported. The device power dissipation is increased by a factor of 100 due to the defects.

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The dynamic operation of a 4H-SiC IGBT turn-off performance is investigated using reported measurements of the interface defect density and device simulation. During the off-state of a repetitive pulse switching, trapped carriers influence the channel potential towards the collector side that creates a path for current flow. The current is observed as an additional tail current that contributes to power dissipation The capture cross-section parameter used in the simulation depicts the probability of traps capturing carriers. Lower parameter value entails longer time for carrier trap/detrap process, and vice-versa. Future scaled SiC-based devices need to achieve an excellent SiC/SiO 2 interface to achieve low off-state current and thereby, low power loss.