The authors report the enhancement of transconductance in nanowire field effect transistors due to build-up tensile stress during thermal oxidation. To evaluate the effect of stress, nanowires were thermally oxidized at (A) 900°C∕15min, (B) 850°C∕1h, and (C) 850°C∕1h with a subsequent 1000°C annealing. The transconductance of sample B is enhanced 2.6 times compared to sample A. No enhancement of transconductance is observed in sample C. The Raman spectra indicate tensile stress in sample B and compressive stress in sample C. This establishes that gm enhancement is due to the build-up tensile stress in nanowires, but is diminished by viscoelastic relaxation.

Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation reveal predominantly horizontal tensile stress in the nwFET channels. The Raman lines in the strain controlled devices display an increase in the full width half maximum, and a shift to lower wavenumber confirming that gm enhancement is due to tensile stress introduced by the PADOX approach.

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Diffusion of phosphorus is studied by means of electrical measurement of the Si-wire devices and SIMS profiles of bulk SOI. The conductivity of Si-wire decreases as the thermal budget increases. The sample of 80nm in the designed width (W mask ), of which the actual width after the oxidation is 57.4nm, has higher conductivity, which is the factor of 3 to 4.5, with respect to the theoretical value of bulk Si. We assume that the stress applied from the peripheral SiO 2 influence on the phosphorus diffusion in Si. Segregation of phosphorus ions at both cap-SiO 2 /Si(SOI) and Si(SOI)/SiO 2 (BOX) is recognized, however, no dependency of SIMS profiles on the thermal budget is confirmed. Dose loss of phosphorus due to the diffusion into the cap-SiO 2 is about 1*10 19 cm -3 . The result of dependency of conductivity on the thermal budged doesn't coincide with the data of SIMS profiles. This is because the SIMS profile of bulk sample doesn't provide the lateral information nor reflect the effect of stress from the peripheral SiO 2 film. Further investigation will be needed to reveal the relation between the size effect on the conductivity and the stress from the peripheral SiO 2 . I. IntroductionAs we all know from the famous prediction for the micron order transistor era, which Gordon Moore predicted, the performance of transistors improved exponentially [1], but it doesn't quite follow his prediction by simple shrinkage. The performance of hp10nm generation transistors is governed by the brand new approaches, so called "technology boosters", such as multiple-gate, ultrathin body (UTB) MOSFET, high-k gate dielectric, metal gate electrode, strained-Si, and non-planar structure. By implementing these "technology boosters", we can expect suppression of gate leakage current, threshold voltage (V th ) control and mobility enhancement even with the further scaling. However, very high-precision of V th control for suppressing the statistical fluctuation of gate current will be required for the hp10min generation, and it is only possible for such a finite adjustment of V th by the conventional method, channel doping, even if V th can be roughly controlled by modifying the work function of the metal gate and by the multiple gate structure. Here, however, a new challenge arises for the ion implantation. Due to the existence of dielelctric/Si interfaces around the channel, dopant ions implanted in Si for the fine adjustment of V th , may diffuse into the dielectric film side, resulting V th control failure. It is well known that SiO 2 act as the sink of the dopant ions and those ions are electrically inactive [5][6][7][8]. Up until now, dopant loss at the Si/SiO 2 interface has been studied intensively [2]- [8]. Macroscopic understanding of dopant diffusion is well achieved, but none has been reported in nano-scale Si, where electrical inactivation due to the dopant trapping, Si/SiO 2 interface effect and strain from peripheral dielectric films give significant effects on the electrical properties in nano-scale Si. We hereby discus...

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