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We report on a recently developed superior ITO-alternative transparent conductor, based on metal mesh technology. Trademarked by Rolith, Inc as NanoWeb ® , metal mesh has the narrowest lines on the market (< 1 micron), which assures complete invisibility of the mesh under the most strict illumination conditions. It has also removed the necessity to optimize metal mesh design for each display structure, since it does not create a visible Moiré fringes, as do other metal mesh conductors on the market. We report also on "best-in-class" optical, electrical and mechanical performance of NanoWeb conductor fabricated on glass plates and PET films.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes.Step and Flash Imprint Lithography (S-FIL TM ) is a unique method for printing sub-100 nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates.With respect to inspection, although defects as small as 70 nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz.Three different experiments were performed. In the first study, large (350 -400 nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70 nm. Using a pixel address of 3 nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200 mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.