Although Li/CF x and Li/CF x MnO 2 have two of the highest energy densitiesof all commercial lithium primary batteries known to date, they are typically current-limited and therefore are not used in highpower applications. In this work, a Li/CF x MnO 2 battery (BA-5790)was hybridized with a 1,000 F lithium ion capacitor to allow its use for portable electronic devices requiring 100 W one-minute pulses. An intelligent, power-management board was developed for managing the energy flow between the components. The hybrid architecture was shown to maintain the battery current to a level that minimized energy loss and thermal stress. The performance of the Li/CF x MnO 2 hybrid was compared to the standard Li/SO 2 battery (BA-5590). The hybrid was shown to deliver the same number of 100 W pulse cycles as two BA-5590 batteries, resulting in a weight savings of 30% and a volumetric reduction of 20%. For devices requiring 8 hours of operational time or less, a 5-cell Li/CF x MnO 2 hybrid was found to be a lighter (55%) and smaller (45%) power source than the existing two BA-5590 battery option, and a lighter (42%) and smaller(27%) option than1½BA-5790batteriesalone. At higher power requirements (>100 W), further weight and size improvements can be expected.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes.Step and Flash Imprint Lithography (S-FIL TM ) is a unique method for printing sub-100 nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates.With respect to inspection, although defects as small as 70 nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This paper reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Ultimately, the most desirable solution is to directly inspect the fused silica template. This paper also reports the results on the first initial experiments of direct inspection fused silica substrates at data rates of 200 MHz.Three different experiments were performed. In the first study, large (350 -400 nm) Metal 1 and contact features were imprinted and inspected as described above. Using a 12 nm pixel address grid, 24 nm defects were readily detected. The second experiment examined imprinted Metal 1 and Logic patterns with dimensions as small as 70 nm. Using a pixel address of 3 nm, and a defect threshold of 20 nm, a systematic study of the patterned arrays identified problem areas in the design of the pattern layout. Finally, initial inspection of 200 mm fused silica patterned substrates has established proof of concept for direct inspection of imprint templates.

Lithography costs for IC production at resolutions of 65-nm and beyond have grown exponentially for each technology node and show no sign of slowing.Step and Flash Imprint Lithography (S-FIL™), developed at the University of Texas (UT) uniquely offers IC manufacturers the potential for lower cost of ownership, because S-FIL does not require expensive optics, advanced illumination sources or chemically amplified resists (CAR). The SIA's addition of Imprint Lithography to the International Technology Roadmap for Semiconductors (ITRS) in 2003, indicates the promise to become a preferred technology and has some compelling advantages over traditional 4X optical lithography.Advanced 90nm binary & phase shift mask processes have been altered using thin Cr (15-nm) & thin e-beam resist (<150nm) resulting in sub 100-nm geometries necessary for S-FIL, and have become the baseline for template manufacture. Commercial production of advanced 1X templates requires CD metrology capability beyond the equipment typically used in 4X mask making. Full commercialization of Imprint Lithography requires not only the ability to generate a 1X template but also a metrology solution that can characterize critical dimension (CD) parameters of the template. Previous published work on S-FIL has focused mainly on high resolution templates produced on 100keV Gaussian pattern generators (PG), and has shown that resolution is only limited by the template 1,2,3 .This work demonstrates that an advanced commercial photomask facility can fabricate templates with sub-100 nm critical dimensions, and that the CDs can be characterized using a commercially available CD-SEM metrology tool. CD metrology repeatability of 0.7nm 3σ was established on a quartz only template with a 6025 form factor.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes.Step and flash imprint lithography ͑S-FIL™͒ is a unique method for printing sub-100-nm geometries. Relative to other imprinting processes S-FIL has the advantage that the template is transparent, thereby facilitating conventional overlay techniques. Further, S-FIL provides sub-100-nm feature resolution without the significant expense of multielement, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. With respect to inspection, although defects as small as 70 nm have been detected using optical techniques, it is clear that it will be necessary to take advantage of the resolution capabilities of electron beam inspection techniques. This article reports the first systematic study of die-to-database electron beam inspection of patterns that were imprinted using an Imprio 250 system. The die-to-database inspection of the wafers was performed on an NGR2100 inspection system. Metal 1 and logic patterns with dimensions as small as 70 nm were inspected. Using a pixel address of 3 nm and a defect threshold of 20 nm, problem areas in the design of the pattern layout were clearly identified. Ultimately, the most desirable solution is to directly inspect the fused silica template. This article also reports the results on the first experiments of direct inspection fused silica substrates at data rates of 200 MHz.

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