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Abstract-The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and program state, respectively. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the sub-threshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present a ReRAM-based non-volatile flipflop which is optimized for sub-VT operation. Writing to the ReRAM devices works with a CMOS-compatible supply voltage. Thanks to near-VT and sub-VT operation and as compared to the write energy, which depends on the ReRAM technology, the read consumes only 5.4% of the total read+write energy. Monte Carlo simulations accounting for parametric variations in both the MOS transistors and the ReRAM devices confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV, and a standard deviation of up to 5% of the nominal value of the ReRAM resistance.

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SUMMARYA continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to efficiently convert subthreshold current to digital code without performing current-to-voltage conversion. As a benefit of this technique, the current-sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low-power and low-voltage current-mode sensor interfaces. The prototype design is implemented in a 0.18 μm standard complementary metal-oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current-sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current-mode analog-to-digital converter designs and is comparable with the voltage-mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current-mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current-mode output in ultra low-power conditions and is also suitable to perform on-chip current measurements in power management circuits.

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