This paper deals with algorithms concerning arithmetic expressions used in a FORTRAN IV compiler for a HITAC-5020 computer having n accumulators. The algorithms generate an object code which minimizes the frequency of storing and recovering the partial results of the arithmetic expressions in cases where there are several accumulators.

In this paper, we present a new scalar architecture for high-speed vector processing. Without using cache memory, the proposed architecture tolerates main memory access latency by introducing slide-windowed floating-point registers with data preloading frmture and pipelined memory. The architecture can hold upward compatibility with existing scalar architectures.In the new architecture, software can control the window structure. This is the advantage compared with our previous work of registerwindows. Because of this advantage, registers are utilized more flexibly and computational efficiency is largely enhanced. Furthermore, this flexibility helps the compiler to generate efficient object codes easily.We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed architecture reduces the penalty of main memory access better than an ordinary scalar processor and a processor with cache prefetching. The proposed architectwe with 64 registers tolerates memory access latency of 30 CPU cycles. Compared with our previous work, the propmkd architecttie hides longer with fewer registers.

No abstract

No abstract

No abstract