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An approach to the implementation of a neural network for real-time cryptographic data protection with symmetric keys oriented on embedded systems is presented. This approach is valuable, especially for onboard communication systems in unmanned aerial vehicles (UAV), because of its suitability for hardware implementation. In this study, we evaluate the possibility of building such a system in hardware implementation at FPGA. Onboard implementation-oriented information technology of real-time neuro-like cryptographic data protection with symmetric keys (masking codes, neural network architecture, and matrix of weighting coefficients) has been developed. Due to the pre-calculation of matrices of weighting coefficients and tables of macro-partial products and the use of tabular-algorithmic implementation of neuro-like elements and dynamic change of keys, it provides increased cryptographic stability and hardware–software implementation on FPGA. The table-algorithmic method of calculating the scalar product has been improved. By bringing the weighting coefficients to the greatest common order, pre-computing the tables of macro-partial products, and using operations of memory read, fixed-point addition, and shift operations instead of floating-point multiplication and addition operations, it provides a reduction in hardware costs for its implementation and calculation time as well. Using a processor core supplemented with specialized hardware modules for calculating the scalar product, a system of neural network cryptographic data protection in real-time has been developed, which, due to the combination of universal and specialized approaches, software, and hardware, ensures the effective implementation of neuro-like algorithms for cryptographic encryption and decryption of data in real-time. The specialized hardware for neural network cryptographic data encryption was developed using VHDL for equipment programming in the Quartus II development environment ver. 13.1 and the appropriate libraries and implemented on the basis of the FPGA EP3C16F484C6 Cyclone III family, and it requires 3053 logic elements and 745 registers. The execution time of exclusively software realization of NN cryptographic data encryption procedure using a NanoPi Duo microcomputer based on the Allwinner Cortex-A7 H2+ SoC was about 20 ms. The hardware–software implementation of the encryption, taking into account the pre-calculations and settings, requires about 1 msec, including hardware encryption on the FPGA of four 2-bit inputs, which is performed in 160 nanoseconds.

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Technical systems in the modern global world are rapidly evolving and improving. In most cases, these are large-scale multi-level systems and one of the problems that arises in the design process of such systems is to determine their reliability. Accordingly, in the paper, a mathematical model based on the Weibull distribution has been developed for determining a computer network reliability. In order to simplify calculating the reliability characteristics, the system is considered to be a hierarchical one, ramified to level 2, with bypass through the level. The developed model allows us to define the following parameters: the probability distribution of the count of working output elements, the availability function of the system, the duration of the system’s stay in each of its working states, and the duration of the system’s stay in the prescribed availability condition. The accuracy of the developed model is high. It can be used to determine the reliability parameters of the large, hierarchical, ramified systems. The research results of modelling a local area computer network are presented. In particular, we obtained the following best option for connecting workstations: 4 of them are connected to the main hub, and the rest (16) are connected to the second level hub, with a time to failure of 4818 h.