We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated. Introduction Phase change memory (PCM) is widely considered to be a potential next-generation non-volatile solid-state memory [1-3]. In addition to its superior write speed compared to 0.2pm -flash, PCM offers a large signal margin between its -crystalline and amorphous states. This wide dynamic range Fig. 2: TEM image of phase-change element (PCE), with underlying also opens the door for multi-level cells (MLC). In this paper, TiN heater on top of W contact. The phase-change material and the we explore MLC write algorithms for up to 16 levels in small o T test arrays, and then demonstrate a 4-level, 32kbit page being overln Tiner are coNnected ubinEs thr a via.part of an experimental memory chip. transferred into the TiN layer using RIB. After strip, oxide isolation is deposited and planarized, exposing the top of the Integration Scheme pillar electrode. The Ge2Sb2Te5 and TiN top electrode layers The memory cell consists of a pillar-heater phase change are then deposited, patterned into islands and encapsulated element (PCE) in series with an access nMOSFET (180nm with dielectric. Top contacts and metallization lines are CMOS technology). As shown in Fig. 1, the 50nm bottom formed using a standard Cu damascene process. Fig. 2 shows electrode heater is fabricated in a subtractive process from a a TEM cross-section of the finished pillar-heater PCE. 75nm thick TiN layer directly deposited over the W contacts.