Since solar energy generation is getting more and more important worldwide PV systems and solar parks are becoming larger consisting of an increasing number of solar panels being serially interconnected. As a consequence panels are frequently exposed to high relative potentials towards ground causing High Voltage Stress (HVS). The effect of HVS on long term stability of solar panels depending on the leakage current between solar cells and ground has been first addressed by NREL in 2005 [1). This potential degradation mechanism is not monitored by the typical PV tests listed in lEG 61215 [2). Depending on the technology different types of Potential Induced Degradation (PIO) occur. This paper is focusing on PIO of wafer based standard p-type silicon technology aiming on increasing life times for solar panels once exposed to external potentials in the field. A test setup is presented for simulation of the PIO in the lab and the influence of cell properties on PIO is demonstrated in order to reveal the cell being the precondition for the PIO. However, PIO can also be stopped or minimized on panel and system level as shown in the paper. BACKGROUND

The aluminum induced layer exchange (ALILE) process allows the formation of thin polycrystalline Si (poly-Si) layers of large grain size on foreign substrates such as glass at low process temperatures. This paper is devoted to a computer simulation study of the kinetics of the ALILE process taking into account the mechanisms of its separate stages: Si diffusion in the AlOx membrane, nucleation and growth of grains, and the formation of preferential (100) orientation. The characteristics of the ALILE process are explained based on the evolution of the Si concentration within the Al layer. In particular it is demonstrated that the characteristic suppression of nucleation after short annealing times results from a decrease in the Si concentration in the Al layer due to the growth of existing grains. A number of important parameters of ALILE process are estimated comparing the results of simulation to the experimental data.

Abstract-To test reproducibility of a technical specification under development for potential-induced degradation (PID) and polarization, three crystalline silicon module types were distributed in five replicas each to five laboratories. Stress tests were performed in environmental chambers at 60°C, 85% relative humidity, 96 h, and with module nameplate system voltage applied. Results from the modules tested indicate that the test protocol can discern susceptibility to PID according to the pass/fail criteria with acceptable consistency from lab to lab; however, areas for improvement are indicated to achieve better uniformity in temperature and humidity on the module surfaces. In the analysis of variance of the results, 6% of the variance was attributed to laboratory influence, 34% to module design, and 60% to variability in test results within a given design. Testing with the additional factor of illumination with ultraviolet light slowed or arrested the degradation. Testing at 25°C with aluminum foil as the module ground was also examined for comparison. The foil, as tested, did not itself achieve consistent contact to ground at all surfaces; but methods to ensure more consistent grounding were found and proposed. The rates of degradation in each test are compared and details affecting the rates are discussed.

Different encapsulation materials are investigated in terms of their PID-suppressing properties. In order to identify materials with a high potential for PID suppression, PID testing was conducted according to test protocols covering system voltages up to 1500 V and particularly long exposure times. Volume resistivity measurements at different temperatures and relative humidity are presented for the different encapsulation materials using "fresh" and aged samples to simulate relevant field conditions and to correlate with PID test results and field findings.

We present a comprehensive overview over infrared imaging techniques for (electrical) silicon solar cell characterization. Recent method development in local series resistance imaging is reviewed in more detail and new results in local breakdown investigations on multicrystalline (mc) silicon solar cells are reported. We observe local junction breakdown sites on industrial mc-cells at reverse voltages as low as -7V and breakdown in great areas of the cell at voltages around -14V. As these breakdown sites (as well as local shunts) can cause hot spots which can damage the cell and the module, we also present an ultra-fast, simple and quantitative method for hot-spot detection. Typical measurement times in the order of 10 milliseconds are achieved