The system design of a locally connected competitive neural network for video motion detection is presented. The motion information from a sequence of image data can be determined through a two-dimensional multiprocessor array in which each processing element consists of an analog neuroprocessor. Massively parallel neurocomputing is done by compact and efficient neuroprocessors. Local data transfer between the neuroprocessors is performed by using an analog point-to-point interconnection scheme. To maintain strong signal strength over the whole system, global data communication between the host computer and neuroprocessors is carried out in a digital common bus. A mixed-signal very large scale integration (VLSI) neural chip that includes multiple neuroprocessors for fast video motion detection has been developed. Measured results of the programmable synapse, and winner-takes-all circuitry are presented. Based on the measurement data, system-level analysis on a sequence of real-world images was conducted.

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An extendable VLSI neuroprocessor chip has been designed with a silicon area of 4.6x6.8 mm2 in MOSIS 2-micron CMOS Smallchip 64-pin package. Computing of optical flow using one neuroprocessor chip can be accelerated by a factor of 8.3 than a Sun-4/260 workstation. Real-time optical flow processing on industrial images is practical using an extended array of VLSI neuroprocessor chips. The mixed analog-digital design techniques are utilized to achieve compact and programmable synapses with gain-adjustable neurons for massively parallel neural computation. Electronic annealing through the control of neurons' gain helps to efficiently search the optimal solutions. Actual examples on moving trucks are presented. ' .

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Real-time digital image restoration using massively parallel Hopfield neural chips is presented. An efficient mixed-signal VLSI design with analog circuitry to perform neural computation and digital circuitry to process multiple-bit pixel information greatly reduces the network size. Analog programmable synapse cells of 8-bit accuracy are dynamically refreshed. The gain-adjustable neurons enable electronic annealing to quickly reach global minimum in energy function. A prototype 25-neuron chip occupies a silicon area of 4.6 x 6.8 m m 2 in MOSIS 2-pm CMOS process has been designed and tested. The speedup factor is 9Ox to Sun-3 workstation for each chip. An 100-neuron image restoration chip is achievable in the industrial-level 1-pm technologies. I. IntroductionReal-time restoration of a high-quality image from a degraded recording is of great significance in early vision processing. Image degradation due to optical system aberration, motion, diffraction, and noise can be recovered. The Hopfield neural network with massively parallel architecture [l] is attractive for this application. To fully explore the advantages of the neural network architecture, a mixed analog-digital VLSI design approach is used. The analog circuitry for neuron and synapse implementation provides a compact and high-speed neural computation. Such analog parallel computation includes multiplication, current summation, and the nonlinear thresholding [2]. Digital circuitry is used to implement registers and memories and control logic. In this paper, an artificial neural chip for real-time digital image restoration is described. Each neuron is used to represent multiple-bit gray level information. The secret is to use the neuron result as an incremenddecrement information to control the pixel register. The result of the pixel register is combined in the synapse array with a distributed digital-to-analog conversion operation. This architecture reduces the number of neurons by a factor of M in the M gray levels image processing. The system-level results show that a 90x speedup to Sun-3 workstation can be achieved.