In this paper, an effective approach to the design of reduces the capacitance spread by trading off sensitivity. large time constants implemented with switched-capacitor (SC) techniques for use in low-frequency signal processingThe problem is more pronounced in modemn CMOS applications, is presented. The proposed method utilizes a nonprocesses. As the minimum channel length Lmin is scaled uniform sampling scheme, which adds one degree of freedom down into the submicron range, the size of operational in obtaining the time constant of SC integrators. As a result, amplifiers and switches is made smaller. However, the capacitor spread and total capacitor area are reduced and, capacitance per unit area is not scaled as l/Lmin and, hence, hence, silicon area can be minimized. To prove the feasibility of the size of the SC filter is mainly determined by the capacitor the presented approach, the design and the implementation of area. Moreover, since the digital circuitry usually requires a second-order lowpass notch SC filter are discussed.only a single polysilicon (poly) layer for the gates, Experimental results from a 0.35-,tm CMOS test-chip that conventional double-poly capacitors are generally not operates at 2 kHz sampling frequency are presented.available in low-cost fabrication processes for digital applications. The second polysilicon layer can be avoided by using poly-to-metal, metal-to-metal or special poly-to-metalto-metal sandwich structures. Nevertheless, the ensuing The switched-capacitor (SC) technique is a very popular capacitance per unit area is lower than the capacitance per analog approach for the implementation of high-precision unit area of a standard double-poly capacitor. Recently, there filtering functions in integrated circuits. However, several have been several attempts to use the gate-to-channel difficulties arise in designing SC filters for very lowcapacitance of MOSFET's to implement capacitors in SC frequency applications (less than 100 Hz). The most serious circuits [5]. Unfortunately, the performance of such problem comes from the need for implementing very large capacitors suffers from the strong voltage dependence of time constants, which leads to large silicon area when using their capacitance, which limits the capacitance per unit area conventional design techniques. to about 0.4 fF/4m2. This value is several times lower than the capacitance per unit area of double-poly capacitors (e.g., To overcome this problem, several approaches for the tretmslwrfrteAS03-~mCO rcs) design of area-efficient SC integrators with very large time three tfmes lower for the AMS 0.35-efm CMOS process). constants have been reported [I]- [4]. The most popular low-freqenc order to realnze area-efficient SC circuits for approach has been the T-network approach [1], which can I a n I be viewed either as a way of reducing the effective input proposed to reduce the capacitance spread.capacitance of the integrator, or as a way to reduce the input In this paper, the design of an SC integrator with a voltage through...

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This paper describes an area-efficient switchedcapacitor sine-wave oscillator for on-chip analog testing. At the core of the oscillator is a bandpass filter (BPF) whose input signal is generated by using a noise-shaping modulation scheme. As a result, the spectral content of the input signal is improved with respect to a conventional BPF-based oscillator and, hence, the spurious-free dynamic range of the sine-wave signal is enhanced. Results from a 0.35-μm CMOS design are presented.

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