In this letter, a CMOS-compatible silicon-oninsulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi 2 salicide with SiO 2 /Si 3 N 4 dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 µm. For the shortest 0.25-µm gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications. Index Terms-Breakdown voltage (BV), cutoff frequency f T , laterally diffused MOS (LDMOS), maximum oscillation frequency f max , RF, salicide.

Novel integration structures of SO1 LDMOSINMOSlinductorlcapacitorIresistor for RFIC are proposed, combined with several key techniques, including body contact with asymmetrical source/drain junctions, Si02/Si3N4 dual Sidewalls and Ti-Sailicide, etc. These devices are integrated into the SlMOX substrate with simplified process steps. Experimental or simulated results show that floating body effects are well restrained, and DC characteristics are good, while the cutoff frequency of LDMOS is higher than that of conventional devices with lateral body-contact structures.