22FDX TM is the industry's first FDSOI technology double-patterning steps required at the 16/14nm FinFET architected to meet the requirements of emerging mobile, technology nodes. Approximately 75% of the process steps Internet-of-Things (IoT), and RF applications. This platform are common with the 28nm platform enabling high yield achieves the power and performance efficiency of a 16/14nm capability. The gate-first High-K Metal Gate (HKMG) FinFET technology in a cost effective, planar device integration is used to ensure a low cost process flow [3]. A architecture that can be implemented with ~30% fewer typical cross-section of nFET and pFET devices is shown in masks. Performance comes from a second generation FDSOI Fig.1. All active devices are built on SOI whereas passive transistor, which produces nFET (pFET) drive currents of devices and select active devices, such as LDMOS, are 910μA/μm (856μA/μm) at 0.8V and 100nA/μm Ioff. For conventionally formed in the bulk substrate (Fig.2). In ultra-low power applications, it offers low-voltage operation addition to the introduction of FDSOI substrates, new process down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and modules are introduced to support back-bias capability, 0.52V V min for high-density and high-current bitcells, ultra-passive device fabrication, enhanced device performance and low leakage devices approaching 1pA/µm Ioff, and body-technology scale factor (Fig.3). The introduction of a SiGe biasing to actively trade-off power and performance. channel for pFET devices by the condensation technique [4] Superior RF/Analog characteristics to FinFET are achieved and SOI thickness <7nm enable high DC drive currents. A including high f T /f MAX of 375GHz/290GHz and post STI hybrid etch process is used to form back gate 260GHz/250GHz for nFET and pFET, respectively. The contacts and enable the implementation of devices and taphigh f MAX extends the capabilities to 5G and millimeter wave cells in the bulk substrate (Fig.4). Dual in-situ doped epi (>24GHz) RF applications. processes (Si:P and SiGe:B) are formed in combination with a low-k spacer to ensure highly doped source/drain regions I. INTRODUCTION while maintaining low gate-to-drain capacitance (critical for Rising manufacturing costs and emerging applications RF applications). Technology CPP is scaled without adding requiring unparalleled energy efficiency are driving the need extra masking steps relative to the 28nm Front-End-of-Line. for new semiconductor device solutions. For the first time, Dual patterning techniques are used to scale M1/M2 pitch, an increase in the cost per die is observed with the leading to a logic/SRAM die scaling of 0.72x/0.83x relative to introduction of 16/14nm FinFET technologies due to the 28nm Poly/SiON technology node. increased process complexity and mask count. Cost sensitive B. Device Performance IoT and mobile applications are driving new requirements such as increased integration, advanced power management, Device construction utilizes either flip well (SLVT/LV...

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Sub-40nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12 % and 10 %, respectively, resulting in performance at 1.0 V and 100 nA/µm IOFF of NIDSAT = 1354 µA/µm and PIDSAT = 857 µA/µm. Product-level implementation of asymmetric transistors showed a speed benefit of 12 %, at matched yield and improved reliability.

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

A major challenge for the application of strain engineering to enhance the performance of electronic devices is the quantification of strain on the nanoscale. Besides other techniques (Raman spectroscopy, X‐ray diffraction) electron beam techniques allow strain analyses with a spatial resolution of a few nanometers and a reasonable strain sensitivity of 1 × 10–3 (relative to the lattice constant of silicon). In the present work, we address practical issues in the application of nano‐beam electron diffraction (NBED) to probe the strain in strained silicon layers and sub‐100 nm structures. The investigated specimens were prepared on biaxially tensile strained silicon‐on‐insulator substrates with an initial strain of ε = 0.6% or 0.8%. Results of the NBED experiments were compared to data obtained by other strain measurement techniques; amongst them the strain mapping by peak‐pairs analysis of high‐angle annular dark field (HAADF) images was especially considered (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)