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Electromigration-induced failure of on-chip interconnects continues to be a problem for the microelectronics industry. The electromigration failure rate of a population of similar lines is sensitive to statistical variation in the microstructural characteristics from line to line. These microstructural details depend upon the process and thermal history of the line as well as on the feature size (line length and width). Moreover, as the widths of interconnect lines have fallen below the median grain size of the films from which they are patterned, two distinct types of failure mechanisms have been observed. Determining which failure mechanism(s) will be observed, and in what proportion, is a crucial concern of reliability engineers. This article investigates the complex dependence of the dominant failure mechanism and overall reliability on process history, minimum feature size, line type, line microstructure, and line test conditions. A grain growth simulator has been used to model the microstructural evolution of a film during processing, both prior to and after patterning. In this fashion, large populations of lines with realistic microstructures have been generated in order to observe statistical differences in microstructure and failure rate. An electromigration model is then used to calculate stress evolution. By assuming a critical stress at which the line fails, the failure distributions and overall reliability of the interconnects are obtained, and the conditions under which a transition-in-failure mechanism will occur are predicted.

The origins of two types of electromigration failure models are explored starting with the basic transport differential equations including the effects of electromigration-induced mechanical stress. We compare the results of a nucleation model, in which failure is determined by the time required to build up a critical stress or a critical vacancy concentration at a site of atomic flux divergence, with a void-growth model, in which failure is linked to the growth of a void to a critical size. Two particular applications of the model are investigated, and the results are shown to be in good agreement with available experimental data. In one example, the effect of the presence of a field-free reservoir region extending beyond the current-carrying region of the line is compared to the case without such a field-free extension. In the other, the effects under pulsed dc current stress are examined in comparison to dc current. Possible applications of this model to design verification are also discussed.

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