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The paper presents the results of design, implementation and adjusting of the CMOS version of the hardware -to-digit converter (IC ADC). There are presented the concept of intelligent conversion, main principles of practical implementation, main stages and particularities of design and adjusting the IC ADC.

The paper presents a brief survey of new results in the theory, modelling, implementation and testing of new class of high-efficient low-energy cyclic A/D converters (CADC) -"intelligent" cyclic ADC (IC ADC). There are discussed general principles of IC ADC functioning, analysis and design, Advantages of IC ADC over conventional CADC caused by transition to computing of the long-bit codes (estimates) of the input signal are explained. Special attention is paid to particularities and methods of modelling analysis and testing of IC ADC.

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