In this work, biaxial and uniaxial strain techniques are implemented in the channel for both p-and n-type FinFETs necessary for advanced CMOS applications. Stress/strain mapping in strained-Si (n-type) and strained-SiGe (p-type) channels (in trapezoidal tri-gate FinFET devices) are studied through three-dimensional (3D) numerical simulation, with particular focus on the enhancement of drain current. Following the strain/stress profiles simulated, the piezoresistive changes are implemented in the simulator to describe the strain effects on device operation. Further, we have investigated the impacts of random discrete dopant variability on the characteristics of a 14-nm gate length FinFET transistors (both n and p-type) using a 3D finite element quantum corrected drift-diffusion device simulator. We have also found the fluctuation of critical device parameters such as threshold voltage (VTH), sub-threshold slope (SS), on current (ION), and off state current (IOFF), etc., mainly originated from the randomness of distribution of the dopants.

In the first part of this work, using TCAD simulations, we examine the breakdown voltage as a function of field plate geometry. In the second part, we show that field plate-based GaN HEMT structures can be optimised to have effectively reduced undesirable parasitic capacitances to greatly improve both the high transconductance and current gain cut-off frequency simultaneously. We report a new generation of high performance AlGaN/GaN HEMTs grown on high resistivity SiC substrates. We examine the small signal and large signal device performances against technological parameters such as the gate length, field plate length, and the source-drain contact separation. The device with a gate length of 0.25 μm and field plate length of 0.3 μm exhibits a maximum dc drain current density of 3.66 A/mm at VGS = 3 V with an extrinsic transconductance of 233.6 mS/mm and an extrinsic current gain cut-off frequency (f t ) of 78.9 GHz.

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