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We propose a built-in scheme for generating all patterns of a given deterministic test set T . The scheme is based on grouping the columns of T , so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM) with log 2 ri flip-flops. As all FSMs run through their states, all patterns of T are generated in time R. Experimental results show that with appropriate filling of the don't cares to reduce the number of representatives in each segment, and with the use of standard sequential synthesis tools, the scheme can offer low hardware overhead as well as low number R of test cycles.

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Two-dimensional scan design is a widely used BIST a, |=°11111I1100100 architecture for pseudo-random and pseudo-exhaustive testing. 2 =°o 1 1 1 1 o 1 o 1 1 oo 1 o However, linear dependencies that arise due to the properties of the test-pattern generators in use have a negative impact a3 = o 1 000 I1 Io 1 o 1 1o on fault coverage. To alleviate this problem, networks of XOR a, gates known as phase shifters are often used. Existing techniques _F (b) for selecting phase shifts, such as those based on large channel S= = separations, lead to inadequate removal of linear dependencies. In Sca ch C this paper we present for the first time a method for the selection T of appropriate channel phase shifts to explicitly minimize linear dependencies. Experimental results corroborate the effect of the approach in increasing fault coverage.