Deterministic Built-in TPG with Segmented FSMs

Abstract

We propose a built-in scheme for generating all patterns of a given deterministic test set T . The scheme is based on grouping the columns of T , so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM) with log 2 ri flip-flops. As all FSMs run through their states, all patterns of T are generated in time R. Experimental results show that with appropriate filling of the don't cares to reduce the number of representatives in each segment, and with the use of standard sequential synthesis tools, the scheme can offer low hardware overhead as well as low number R of test cycles.

Stochastic Approach to Test Pattern Generator Design

“…In (Garbolino & Papa, 2008;2010) a Multi-Input Signature Register (MISR) is combined with a combinational logic which modifies its state diagram in such a way that the MISR generates a sequence of expected deterministic test patterns. A method of designing a deterministic TPG based on non-uniform CA was proposed in (Cao et al, 2008), while another solution employs a group of small Finite State Machines (FSMs) to generate a relatively short vector sequence that contains all deterministic test patterns (Sudireddy et al, 2008). The proposed LFSR structures are based on D-type flip-flops, while in recent years LFSR composed of D-type and T-type flip-flops or even of T-type flip-flops only, has been gaining popularity.…”

Genetic algorithm for test pattern generator design

“…An interesting method of designing a deterministic TPG based on non-uniform CA was proposed in [5]. Yet another solution employs a group of small Finite State Machines (FSMs) to generate a relatively short vector sequence that contains all deterministic test patterns [38].…”