The extensive research of aggressively scaled nanoelectronic devices necessitates the inclusion of quantum confinement effects and their impact on performance. This work implements a set of multisubband phonon and impurity scattering mechanisms and the Kubo-Greenwood theory in order to study their impact on the mobility in Si nanowire transistors (NWTs). This 1D treatment has been coupled with a 3D Poisson-2D Schrödinger solver, which accurately captures the effect of confinement on charge dynamics. We also emphasize the importance of using the 1D models to evaluate the geometrical properties on mobility at the scaling limit.

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This article is a review of the current progress and results obtained in the European H2020 CONNECT project. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, 2) modeling and simulation from atomistic to circuit-level benchmarking and performance prediction, and 3) characterization and electrical measurements. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a review and informative cornerstone on carbon nanotube interconnects.

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Here, we review and present current challenges and progress on Carbon Nanotube Integration for BEOL Interconnects as well as our recent results. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) improvement of the variability of SWCNTs for local interconnects 2) process & growth of carbon nanotube interconnects compatible with BEOL integration and formation of CNT-copper-composites, 3) modeling and simulation from atomistic to circuit-level benchmarking and performance prediction, and 4) characterization and electrical measurements. The aim is to evaluate the use of CNT-based materials for future metallization, both in regards to manufacturability, i.e. CMOS compatibility and wafer-scale integration as well as realistic performance expectations, i.e. variability and defectivity. I.