No abstract

No abstract

A process independent layout tool for analog integrated CMOS circuits is presented. The tool is able to layout automatically analog cells from netlist information and user-specified constraints. STUCCO

No abstract

This paper reports on simulation techniques developed for the modelling and optimisation of complete, 2 x 2 cm2, high-efficiency silicon solar cells. We use three-dimensional (3d) device simulation to extract a J-V curve of an interior section of a cell. 2D simulations of the cell perimeter are then used to correct the J-V curves for the loss of carriers across the cell boundary. The resulting characteristics are input to a circuit simulation which connects the various cell sections into a model of a full cell. The J-V curve which results from that simulation can be directly compared to measured data. We find excellent agreement between simulation and measurement.