ILAC: an automated layout tool for analog CMOS circuits

Rijmenants, J.; Schwarz, Thorsten; Litsios, J.; Zinszner, R.

doi:10.1109/cicc.1988.20820

Cited by 32 publications

(11 citation statements)

References 5 publications

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“…This area can be user-speci ed or automatically computed as explained in Section III. Parameter i and has the same meaning as in (14). f co (s) is a penalty function accounting for performance constraint violations.…”

Section: Examplementioning

confidence: 99%

“…A variety of approaches inherited from the digital CAD world, with placement based on slicing structures and channel routing, have been proposed: in macro-cell 10] and standard-cell 11], 12], 13] approaches, capacitive coupling between interconnections is minimized during global routing by allocating sensitive nets to separate channels. In ilac 14], the layout generator for the analog synthesis system idac 15] the layout is based on the generation of specialized pre-de ned modules. Knowledge-based approaches, such as the ones presented in salim 16], ladies 17] and blades 18], rely heavily on the user's expertise.…”

Section: Introductionmentioning

confidence: 99%

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Automation of IC layout with analog constraints

Malavasi

Charbon

Felt

et al. 1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

159

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A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and e cient design environment. In the proposed approach, performance speci cations are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design ow. Examples drawn from industrial applications are reported to illustrate the e ectiveness of the approach. Keywords| Layout, Analog Design, Constraint-Driven Layout.

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Section: Examplementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automation of IC layout with analog constraints

Malavasi

Charbon

Felt

et al. 1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

159

View full text Add to dashboard Cite

show abstract

“…This strategy also strongly affects the design of the placement algorithms in KOAN: details about design rules, electrical connectivity, parasitic minimization, wells, etc., must be dealt with during placement, since they are not fixed during procedural device generation. Our placement strategy, like some device placers [7], [8], is based on simulated annealing. However, the annealing formulation is considerably more complex, given the new density and electrical performance optimizations we require it to support.…”

Section: Analog Device Placement I N Koanmentioning

confidence: 99%

“…The critical problems involve handling analog-specific constraints that render the layout much more sensitive to low-level geometric choices than digital cells of similar size. Work to date on analog layout has included knowledge-based approaches [4]- [6], al-gorithmic techniques for placement [7]- [ll], routing [7]- [13], compaction [7], [ 141, procedural device and module generation [3], [9], [ 151-[ 171, and performance constraint generation [18], [19]. Our interest is algorithmic placement and routing for custom analog cells.…”

Section: Introductionmentioning

confidence: 99%

“…Our interest is algorithmic placement and routing for custom analog cells. A block place-and-route approach, which we refer to as the macrocell layout style [3], [7], [SI, has emerged as a popular candidate for recent analog cell layout tools: from a netlist, critical primitives (such as matched devices or complex folded structures) are produced by parameterized module generators; these primitive blocks are placed, and then routed. This style is derived from techniques for layout of digital IC's.…”

Section: Introductionmentioning

confidence: 99%

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KOAN/ANAGRAM II: new tools for device-level analog placement and routing

Cohn

Garrod

Rutenbar

et al. 1991

IEEE J. Solid-State Circuits

288

103

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This paper describes KOAN and ANAGRAM 11, new tools for device-level analog placement and routing. A block place-and-route style from macrocell digital IC's has recently emerged as a viable methodology for the automatic layout of custom analog cells. In this nuIcroceU style, parameterized module generators produce geometry for individual devices, a placer arranges these devices, and a router embeds the wiring. However, analog layout tools that merely apply known digital macrocell techniques fall far short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM I1 differ from existing approaches by employing general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk contacts. New routing algorithms implemented in ANAGRAM I1 handle arbitrary gridless design rules in addition to over-the-device, crosstalk avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented.

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A set of device generators for analogue and mixed-signal layout synthesis

Naviner

Loumeau

Oliaei

et al. 1997

VLSI: Integrated Systems on Silicon

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The layout synthesis of analog circuits remains today a complex task difficult to automate. Various strategies are used, from a completely full-custom design up to an automated synthesis taking into account analog constraints. One popular technique developed to help the analog layout synthesis is the use of procedural design of basic cells. These cells are afterwards assembled either manually or using other CAD tools. The device generators described in this paper are developed to enhance layout design productivity of analog cells. These generators are written in language Skill for the Opus-Cadence framework. They cover the most common devices: resistors, capacitors, inductors, various transistor shapes, differential pairs and current sources. The context and the objectives of this work, the development strategy and the main functionalities are presented. Finally, an example is given. These generators have been successfully used to design several circuits.

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ILAC: an automated layout tool for analog CMOS circuits

Abstract: A process independent layout tool for analog integrated CMOS circuits is presented. The tool is able to layout automatically analog cells from netlist information and user-specified constraints. STUCCO

Cited by 32 publications

References 5 publications

Automation of IC layout with analog constraints

Automation of IC layout with analog constraints

KOAN/ANAGRAM II: new tools for device-level analog placement and routing

A set of device generators for analogue and mixed-signal layout synthesis

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