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Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliver the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per bitline, and reduced bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper introduces various circuit techniques for designing robust high-density subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent bitline leakage to enable long bitlines, (iv) virtual ground replica scheme for improved bitline sensing margin, (v) writeback scheme for data preservation during write, and (vi) optimal gate sizing based on subthreshold logical effort. Fig. 18.5.1 shows the proposed 10T SRAM cell. When read is enabled (RWL=1), the read bitline (RBL) is conditionally discharged through pull-down transistors M7, M8, and M9 depending on 'QB'. The cell node is isolated from the bitline during read operation, retaining a hold mode SNM. The 10T SRAM cell has an SNM of 76mV at a supply voltage of 0.2V while that of a conventional 6T SRAM cell is 14mV. When read is disabled (RWL=0), node A is held to V DD making the bitline leakage flow from node A to RBL, regardless of the data stored in the SRAM cell. Write operation of the proposed cell is performed by asserting WWL while the write data are loaded onto the write bitlines (WBL, WBLB). To improve the write margin, previous techniques have applied a wordline voltage that is higher than the cell voltage to increase the drive current of the write access transistors [2]. Instead, we use the governing RSCE in the subthreshold region to improve the cell writability without introducing a separate high V DD . RSCE is observed in modern CMOS devices due to the HALO pocket implants used to compensate the V t roll-off [3]. RSCE is not a concern in conventional superthreshold designs since it does not affect the device characteristics of minimum channel length transistors. However, in the subthreshold region where DIBL is reduced and current depends exponentially on V t , RSCE causes the operating current to increase with a longer channel length, as shown in Fig. 18.5.2. For a fixed device width, minimum delay is achieved at 0.36µm in the subthreshold region, which is three times longer than the minimum channel length of 0.12µm. For equal drive current, device width can be reduced as the channel length is increased, lowering the junction capacitance, which significantly contributes to the write power consumption. Using RSCE yields further advantages such as better sub-threshold slope owing to the longer channel length and reduced impact of random dopan...

A study of field trapping by the incomplete Meissner effect was performed on YBa2Cu3O7−x at 77 K on both sintered and oriented grain samples. Fields of up to BT=1280 G have been trapped in small, oriented grain, planar samples. Circulating persistent current densities of up to 4800 A/cm2 are calculated. Based on these values hollow cylinders of 2 cm i.d. will trap fields of 6000 G. Initial creep is about 10%/week for both types of samples. Creep rate varies as (BT/BT,max)2. BT, due to an external field B0, is BT∝(1−e−cB0/BT,max). Lamination and mosaic assembly steps for producing practical magnets have been performed.

We report on persistent field in a quasipermanent magnet made of high temperature superconductor. The material has an average of 40% molar excess of Y, relative to Y1Ba2Cu3O7 and has been irradiated with high energy light ions at 200 MeV. The magnet, which traps 1.52 T at 77.3 K, traps nearly 4 T at 64.5 K. No evidence of giant flux jump or sample cracking was observed.

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