A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme

Abstract

Robust high-density subthreshold SRAMs are indispensable for emerging ultra-low power applications such as implantable devices, medical instruments, and wireless sensor networks. Conventional 6T SRAMs in the subthreshold region fail to deliver the density and yield requirements due to the reduced static noise margin (SNM), poor writability, limited number of cells per bitline, and reduced bitline sensing margin. 8T and 10T SRAM cells have been proposed to improve the SNM by decoupling the SRAM cell nodes from the bitline and hence making the read mode SNM equal to the hold mode SNM [1,2]. This paper introduces various circuit techniques for designing robust high-density subthreshold SRAMs: (i) decoupled cell for read margin improvement, (ii) utilizing reverse short channel effect (RSCE) for write margin improvement, (iii) eliminating data-dependent bitline leakage to enable long bitlines, (iv) virtual ground replica scheme for improved bitline sensing margin, (v) writeback scheme for data preservation during write, and (vi) optimal gate sizing based on subthreshold logical effort. Fig. 18.5.1 shows the proposed 10T SRAM cell. When read is enabled (RWL=1), the read bitline (RBL) is conditionally discharged through pull-down transistors M7, M8, and M9 depending on 'QB'. The cell node is isolated from the bitline during read operation, retaining a hold mode SNM. The 10T SRAM cell has an SNM of 76mV at a supply voltage of 0.2V while that of a conventional 6T SRAM cell is 14mV. When read is disabled (RWL=0), node A is held to V DD making the bitline leakage flow from node A to RBL, regardless of the data stored in the SRAM cell. Write operation of the proposed cell is performed by asserting WWL while the write data are loaded onto the write bitlines (WBL, WBLB). To improve the write margin, previous techniques have applied a wordline voltage that is higher than the cell voltage to increase the drive current of the write access transistors [2]. Instead, we use the governing RSCE in the subthreshold region to improve the cell writability without introducing a separate high V DD . RSCE is observed in modern CMOS devices due to the HALO pocket implants used to compensate the V t roll-off [3]. RSCE is not a concern in conventional superthreshold designs since it does not affect the device characteristics of minimum channel length transistors. However, in the subthreshold region where DIBL is reduced and current depends exponentially on V t , RSCE causes the operating current to increase with a longer channel length, as shown in Fig. 18.5.2. For a fixed device width, minimum delay is achieved at 0.36µm in the subthreshold region, which is three times longer than the minimum channel length of 0.12µm. For equal drive current, device width can be reduced as the channel length is increased, lowering the junction capacitance, which significantly contributes to the write power consumption. Using RSCE yields further advantages such as better sub-threshold slope owing to the longer channel length and reduced impact of random dopan...

Self-aware computing in the Angstrom processor

“…Conventional SRAMs cannot work at low-voltage levels due to stability problems. Thus, recent work has focused on implementing different bit-cell topologies [7,6] and peripheral assist circuits [21,33] to enable operation down to sub-VT levels.…”

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

“…For example, [10] employed Schmitt-trigger based SRAM cell, enhancing read stability and writability simultaneously. To further increase read SNM, single-end 8T [4] or 10T [3], [5] SRAMs have been explored. In these schemes, data nodes are fully decoupled from read access.…”

“…It ensures read SNM to be almost the same as hold SNM, improving read stability significantly. In addition, several design techniques such as supply power gating [3] and long-channel access transistors [5] also have been proposed for writability improvement. The subthreshold operation of the designs with these techniques has been verified through hardware measurement data as well [3], [5].…”

“…In addition, several design techniques such as supply power gating [3] and long-channel access transistors [5] also have been proposed for writability improvement. The subthreshold operation of the designs with these techniques has been verified through hardware measurement data as well [3], [5]. However, the single-end 8T or 10T SRAMs cannot efficiently deal with multiple bit soft-errors, which can have large impact on SRAM operation in the subthreshold region.…”

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage

“…4(b) is obtained as shown in (7) and (8) at the bottom of the previous page. Comparing (1) and (6), and since , we have that (9) Then, by comparing (2) and (7), we obtain (10) As can be seen, dividing a large transistor into smaller parallelized transistors helps to increase the subthreshold current due to larger mismatch. We also did Monte Carlo simulations to confirm the effectiveness of this approach.…”