Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm 2 /sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm 2 .The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm 2 while preserving high rate capability.

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The HRFlexToT is a 16-channel ASIC for SiPM anode readout designed for Positron Emission Tomography (PET) applications that features high dynamic range (>8 bits), low input impedance, common cathode connection, high speed and low power (≈3.5 mW/ch). The ASIC has been manufactured using XFAB 0.18 µm CMOS technology. The main characteristics of the HRFlexToT, compared to its predecessor, are a new energy measurement readout providing a linear Time Over Threshold (ToT) with an extended dynamic range, lower power consumption and better timing response. Initial measurements show a linearity error below 3%. Single Photon Time Resolution (SPTR) measurements performed using a Hamamatsu MPPC S13360-3050CS (3x3 mm 2 pixel, 50 µm cell) shows 30% improvement with respect to the previous version of the ASIC, setting this specification in the order of 141 ps FWHM and reducing 3 times power consumption. It is important to highlight that an SPTR of 141 ps FWHM is, according to the best of our knowledge, the best resolution achieved so far for this sensor. Coincidence Time Resolution (CTR) measurements are expected to be performed during 2018.