Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

No abstract

No abstract

We study layout dependent, parasitic capacitance contribution of MOSFETs with 3-dim simulations, and show, that these capacitance contributions are for narrow, short devices comparable to intrinsic contributions. We show that the performance of 65-nm technology is strongly affected by these components, and have therefore been modeled correctly in circuit simulations. We propose a methodology how to accurately and consistently model them in a design flow. The methodology is validated with ring oscillator measurements.

No abstract