Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

MechanicaI reliability is widely recognized as the primary obstacle to productization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SO1 substrates.

In the frame of the ALLIANCE program between Motorola, Philips Semiconductors and STMicroelectronics, electron beam direct write (EBDW) lithography based on shaped beam projection is employed to start quickly an aggressive 65 nm program for the printing of all critical levels. This paper reviews the economical opportunities offered by the introduction of electron beam (E-Beam) lithography for prototyping and advanced research and development applications. EBDW process integration capabilities are also demonstrated, confirming after electrical validation, the real possibilities of EBDW solution for application specific on integrated circuit (ASIC) manufacturing.

The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. In this paper, the authors focus mainly on the impact of porous low-k on the interconnect reliability.Numerous reliability issues are induced by the porosity compared to the dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliabiIity, the ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on the porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal fines and dielectric spacings, All of this together has an enormous impact on the reliability of the end product. IntroductionDriven by aggressive technology roadmap requirements and diverse application-driven requirements, the 45nm technology node will require substantial technology development and innovation in device structure, front-end and back-end materials and processes, and lithography

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