As device geometries shrink into the subha1f micron regime, controlling and reducing defect levels becomes increasingly important in both R&D and Manufacturing envirounments. Any delay in addressing the causes and cures ofthese yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to mWology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects ofproposed manufacturing improvements. In this paper, we will discuss a methodology for optimizing an Mine lithographic process with the aid of a photo defect monitor. Clean Silicon wafers were fully processed through a photocluster cell to simulate the actual processing conditions for the product, then inspected on a KLA 2132 for pattern defects. An in4ine low voltage SEM system was used to review and to classify defect types. In a case study presented here, post develop residue was found to be the predominant defect for a new I-line resist used in the backend layers of the 0.25 um process technology. The resolution ofthe resist residue deposition problem was commenced by evaluating different processes with multiple puddles/rinses for their defect densities. Based on this work, a low defect developer process was chosen for further study. Other process variables such as resist profile, CD uniformity and Etch bias as well as electrical defect parameters were compared between the old and the new processes. The goal is to demonstrate that given equal performance in all other respects, a quick implementation ofthis new low defect process, prior to the sort yield confinnation, would not have any detrimental effect on device yield. An example of a non-killer defect, water stain droplets, discovered during the defect review will be shown. Further refining ofthe thy cycle in the process eliminated this cosmetic defect. Finally, the KLA defect trend chart will show an improvement in defect density with the new develop process.

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Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach.