In the upswing of contemporary science we can monitor and regulate the saline flow rate. Scrupulous flow has to be retained so that risks of fore shortening the threshold level of patient’s heart rate, blood pressure and oxygen level in blood level. Intravenous infusion used intermittently in hospital has to be checked for is purity. For the change in threshold level of patient’s body condition, saline flow has to be adjusted. The assessments obtained from the patients is proceed to the centralizer controller which is connected to the cloud is updated periodically to avoid loss of reports. The updated data sets shared to the chemist and CPU so that flow rate of saline is controlled automatically in accordance to the data received. The machine learning based algorithm (SVM) is used to predict the more accurate changes on data which is obtained from patients so that the controller can act agilie. This work gives better results based on the accuracy level calculation and efficiency improvement in terms of more fast response.

In VLSI design power dissipation is an important factor in micro and nano VLSI design. For Space applications, Circuits with Ultralow power (ULP) operation is a good solution because of its limited options of energy sources. This Ultralow power operation will pay the way to small and low-cost satellites where the heavy battery and power supplies can be replaced. One of the effective way to implement ULP operations are by restricting the VDD and make the circuit to work in sub threshold region. But at the same time this low voltage circuits have some challenges like delay, temperature fluctuations needs to be addressed. The most complicated area of these circuits are memory arrays which cover large areas of the silicon die which often store critical data. Large bit cells leads to hardening of embedded memory block cells and this limits the low power operation of the entire system. In this paper, radiation-hardened static random access memory (SRAM) bit cell targeted at low-voltage functionality is proposed. The proposed method employs 5T RAM cell bears changes in charge deposits as high as 500 fC at a scaled 500-mV supply voltage.

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“The technology defined today might be redefined tomorrow”- from the quotes, in the modern era redefining the architecture with the optimization of area, delay and reduction of power is focused more than fixed models. This paper describes the floating point arithmetic unit and insists the importance of it, in real time signal processing. The present trends of portable devices for medical applications need occupancy of smaller area with long span time life of battery. The bio medical signals are converted into IEEE 754 format as BIF. Hence it is easily analyzed in FPGAR devices and also this work insists the importance of redefining the architecture with reduction of critical path delay. The FPU arithmetic unit has the blocks to perform the computations like addition, Multiplication and division operation. The main architecture is constructed using top level design with individual blocks defined as a part of it. The floating point unit defined with modern FPGAR (Reconfigurable FPGA) increase the speed of computation and enables the flexibility and adopted to the hardware reconfigurable models. A 32 bit representation of IEEE 754 results of FPU is stored in the data storage and this process optimize the critical path between blocks. The way its programmed consumes lower level of power consumption in the range of 50.4 nw and delay of 25.2 ns and also modern adder structure with 6T type was used to implement the intermediate blocks of multiplier in FPU block as part of computing partial products. By this process of FPU redefining, reduce the number of slice to 206 and increase the operating frequency of 46.12 MHz.

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