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A physically based methodology is developed for modeling the behavior of electrical circuits containing nonideal ferroelectric capacitors. The methodology is illustrated by modeling the discrete ferroelectric capacitor as a stacked dielectric structure, with switching ferroelectric and nonswitching dielectric layers. Electrical properties of a modified Sawyer–Tower circuit are predicted by the model. Distortions of hysteresis loops due to resistive losses as a function of input signal frequency are accurately predicted by the model. The effect of signal amplitude variations predicted by the model also agree with experimental data. The model is used as a diagnostic tool to demonstrate that cycling degradation, at least for the sample investigated, cannot be modeled by the formation of nonswitching dielectric layer(s) or the formation of conductive regions near the electrodes, but is consistent with a spatially uniform reduction in the number of switching dipoles.

We have identified several features of the 1/f noise and radiation response of metal-oxide-semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e., ‘‘border traps’’ [D. M. Fleetwood, IEEE Trans. Nucl. Sci. NS-39, 269 (1992)]. The effective density of border traps depends on the time scale and bias conditions of the measurements. We show the revised nomenclature can provide focus to discussions of the buildup and annealing of radiation-induced charge in non-radiation-hardened MOS transistors, and to changes in the 1/f noise of MOS devices through irradiation and elevated-temperature annealing. Border-trap densities of ∼1010–1011 cm−2 are inferred from changes in switching-state density during postirradiation annealing, and from a simple trapping model of the 1/f noise in MOS devices. We also present a detailed study of charge buildup and annealing in MOS capacitors with radiation-hardened oxides through steady-state and switched-bias postirradiation annealing. Trapped-hole, trapped-electron, and switching-state densities are inferred via thermally stimulated current and capacitance-voltage measurements. A lower bound of ∼3×1011 cm−2 is estimated for the effective density of border traps that contribute to the electrical response of the irradiated devices. This is roughly 20% of the observed switching-state density for these devices and irradiation conditions. To our knowledge, this represents the first quantitative separation of measured switching-state densities into border-trap and interface-trap components. Possible physical models of border traps are discussed. E′ centers in SiO2 (trivalent Si centers associated with oxygen vacancies) may serve as border traps in many irradiated MOS devices.

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