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Today's deep sub-micron semiconductor technology has enabled large-scale integration of multi-million gates consisting of reusable intellectual property (IP), on-chip memory and user-defined logic on a single chip. The design of such SoC has introduced several challenges in terms of increased design complexity in the areas of functional verification, timing closure, physical design, signal integrity, reliability, manufacturing test and package design. This tutorial will discuss a methodology that is based on the successful design of several digital dominated SoCs such as high-speed low-cost communications Processors, VOP and DSL devices, High performance Audio and Video Processors at Texas Instruments. It will provide a complete breadth of digital chip design techniques. In addition, it will cover some issues related to mixed-signal SoC and hierarchical design. Design tradeoffs will be discussed to handle the SoC complexity, and yet meet the time-tomarket demands. We will review different methodologies that are followed in the industry to design these chips. Following topics will be covered with examples to explain design challenges and the approaches used to address them:Design Planning Functional Verification Design For Test (DFT) Synthesis, Floor-planning, and STA Design Closure Manufacturing Tests Future Challenges degrees. He is managing SoC designs in broadband applications at Texas Instruments, Dallas. He has successfully managed SoC designs in the area of fixed wireless access, voice over packet (VOP), communications processors, and DSL CPE modems. He has published several journal and conference papers in the area of binary and multiple-valued logic VLSI design. He has organized and presented two hands-on tutorials on "Rapid-prototyping of Digital Designs" and a half day tutorial on "SoC Design Methodology". He has also taught several engineering courses at university and technical college levels.

In this tutorial we present a comprehensive analysis of the available clock gate (CG) optimization approaches with recent innovations available in EDA tools as they have developed in time. Based on these approaches, we propose an integrated and additive design methodology spanning the backend design space. We show that over 30% power savings in dynamic power can be achieved through this methodology subject to application scenarios of the design.