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A 3 . W 1 OOMHz BiCMOS 3.3M-transistor microprocessor in 163nim2 makes use of a four-layer metal 0.6pm technology. This device is a n architecturally-equivalent second-generation superset of a previous CPU implemented in 0.8pm BiCMOS technology [l]. It consists of a super scalar integer unit, a floating point unit, and separate 8kB instruction and data cachw. This implementation emphasizes several key areas.First, a new design methodology exploits the four-layer metal proccss to optimize power and clock distribution, while minimizing die area. Second, a clock distribution and control system allows for selective power-down of portions of circuitry when not needed, including a stop-clock or sleep mode. This resuits in a 2x power reduction in actual systems running applications software. Finally, clock synthesis techniques and clock domain transfer mechanisms support several ratios of external and internal clock frequencies. This paper describes the design methodology, circuit techniques, process technology, and overall results achieved.

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