A 3.3V 0.6 μm BiCMOS superscalar microprocessor

Abstract

A 3 . W 1 OOMHz BiCMOS 3.3M-transistor microprocessor in 163nim2 makes use of a four-layer metal 0.6pm technology. This device is a n architecturally-equivalent second-generation superset of a previous CPU implemented in 0.8pm BiCMOS technology [l]. It consists of a super scalar integer unit, a floating point unit, and separate 8kB instruction and data cachw. This implementation emphasizes several key areas.First, a new design methodology exploits the four-layer metal proccss to optimize power and clock distribution, while minimizing die area. Second, a clock distribution and control system allows for selective power-down of portions of circuitry when not needed, including a stop-clock or sleep mode. This resuits in a 2x power reduction in actual systems running applications software. Finally, clock synthesis techniques and clock domain transfer mechanisms support several ratios of external and internal clock frequencies. This paper describes the design methodology, circuit techniques, process technology, and overall results achieved.

Power conscious CAD tools and methodologies: a perspective

“…Fig. 14 shows the differences in current demand between using and not using low power design techniques [93]. Notice how the current differences between peak operation and idle operation are larger in the design using power savings techniques.…”

Power Reduction Through Clock Gating by Symbolic Manipulation

“…This technique is not new at all and already applied in a number of ways. In (Schutz 1994) and (Suessmith etal. 1994) this technique is applied during the design of microprocessors, however the places where the gated-clocks are inserted are determined by the designer.…”

Challenges in low-power microprocessor design

“…power, clock gating (or clock enabling) is one of the most common and effective ways to reduce clock activity [3]. An important concern during implementation of clock gating is that the disabled block may not powewp in time or modified clocks may generate glitches.…”

“…This increases the di/dt demand on the die which can get worse at higher frequencies. Figure 1 shows the differences in current demand between using and not using the clock power down techniques [3,4]. Notice how the differences between peak operation and idle operation are larger when power saving techniques are enabled.…”