The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22µm SOI technology to a 0.18µm SOI technology [1]. Key features of the 0.77 scaled 1.5V technology are 0.08µm NFET channel lengths, 7 layer Cu metallization with low-e dielectric, low dose SOI substrate for improved material quality and productivity, and local interconnect. Dual gate oxide provides high I/O voltage compatibility. As this chip is a migration only 6 levels of metal and stacked devices for high voltage I/O were used.

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We present an application of machine learning to automated robust optimization of electronic circuit design that combines artificial neural networks and global optimization. A neural network regressor is constructed to predict circuit operation metrics such as power, offset, delay, phase margin based on input parameters such as device size, temperature, supply voltage and current, and process corner. This regressor is then used to build an objective function for global optimization to find the optimal set of controllable parameters that optimize the objective function subject to input constraints such as device size range and output constraints such as power consumption or delay. Experimental results from tuning state-of-the-art high performance PLL circuits show that this framework is promising and can in much less time find optimized circuits that outperform circuit designs that were manually tuned by a skilled circuit designer.

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