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An equalization system including clock recovery is presented. Usually, the clock recovery is carried out before equalization because there is a system instability when it is processed after equalization. This equalization system comprises two different parts : a classical part, that is, a Mean Square Error (MSE) time domain equalizer and a specific part. The latter one provides the means of ensuring clock recovery included in the equalizer loop. The main functions are a fixed phase of the sampling clock simulation (FPSCS) and a stop criterion derived from the Bit Error Rate (BER) by using correlation of duobinary data. The results show that the system improves the BER. It can be used to get the required sampling clock and synchronization acquisition, even with severely-distorted signals. The system is stable for all the perturbations induced by the channel transmission for D2-MACPacket signal.

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