Fig. 1 Three workload profiles (cases -A, B, C) applied to a transistor under NBTI stress and the corresponding normalized degradation. During active mode, the frequency (=1GHz) and DF (=0.5) are fixed in all cases.

A two-stage sliding-mode controller design for a singutar perturbation system is investigated in this paper. At first, we design the slow and fast sliding-mode controllers for the subsystems individually. Then we obtain the composite sliding-mode control (SMC). The upper bound problem of the singular perturbation parameter in such control system is also determined. An efficient way of eliminating the chattering is developed. A numerical example [4] is given to demonstrate the proposed schemes. time--sec time-sec Response of z2,hill order(solid line) Response of z1,full order(so1id line) 0.5 y --, time-sec time-sec Fig1 : Simulation results of the closed-loop control system with S = c, 11 and E 4. I Response of x1,full order(solid line) Response of x2,full order(solid line) -0.5 time-sec llme--sec Response of zl,full order(solid line) Response of t2,fulI order(solid line) I 4 , . -0.5, -' ' 5 0 u 0 . '

Mobility is the primary device parameter affecting circuit performance in flexible thin-film transistor (TFT) technologies, and is particularly sensitive to the change of mechanical strain and temperature. However, existing algorithms only consider the impact of mechanical strain in cell placement of flexible TFT circuits. Without taking temperature into consideration, mobility may be dramatically decreased which leads to circuit performance degradation. This article presents the first work to minimize the mobility variation caused by the change of both mechanical strain and temperature. Experimental results show that the proposed algorithms can effectively and efficiently reduce the increasing critical path delay. ACM Reference Format: Lin, J.-L., Wu, P.-H., and Ho, T.-Y. 2014. Placement optimization of flexible TFT circuits with mechanical strain and temperature consideration.

Design margins are necessary to ensure reliable operation of integrated circuits over extreme ranges of environmental variations (Voltage, Temperature) and manufacturing Process variations. On top of these PVT variations, aging related parametric drift (e.g. due to BTI, HCI) also limits performance by requiring additional timing margin. In principle, corner based design methodology can be adopted. However, this approach is sub-optimal, because it applies margins which may be either too optimistic or pessimistic since it tends to ignore the correlation effects which exist inherently due to the circuit topology and the workload effects. In this paper, we propose a workload-dependent reliability aware optimization flow under the influence of NBTI aging by utilizing an optimal margining scheme. The proposed flow takes into account the relevant correlations in a design by modelling the degradation accurately and thus enables achieving the desired Power-Performance-Area (PPA) goals without severe reliability penalty.

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