Challenges of the new nanometer processes have complicated the yield enhancement process. The systematic yield loss component is increasing, due to the complexity and density of the new processes and the designs that are developed for them. High product yields can now only be achieved when process failure rates are on the order of a few parts per billion structures. Traditional yield ramping techniques cannot ramp yields to these levels and new methods are required.This paper presents a new systematic approach to yield loss pareto generation. The approach uses a sophisticated Design-of-Experiments (DOE) approach to characterize systematic and random yield loss mechanisms in the Back End Of the Line (BEOL). Sophisticated Characterization Vehicle (CV)™ test chips, fast electrical test and Automatic Defect Localization (ADL) are critical components of the method. Advanced statistical analysis and visualization of the detected and localized electrical defects provides a comprehensive view of the yield loss mechanisms. In situations where the defects are not visible in a SEM of the structure surface, automated FIB and imaging is used to characterize the defect. The combined approach provides the required resolution to appropriately characterize parts per billion failure rates.

This paper describe the detection of visible and nonvisible defects in 3DIC flows. These new flows have process modules that have been used before in CMOS wafer fabrication. There are opportunities to create latent defects such as via voids or thin insulating films that need to be managed. The ideal approach is 100% electrical test but unfortunately that is not cost effective. Management of these defects using inspections, with the inherent risks due to sampling, and low yield analysis feedback is required. This paper describes the use of traditional optical inspection, fluorescent inspection, acoustic metrology and data analysis to manage these defects.