In this letter, we report about design, fabrication, and testing of echelle grating (EG) demultiplexers in the O-band (1.31-µm) for silicon-based photonic integrated circuits. In detail, flat band perfectly chirped EGs and two-point stigmatic EGs on the 300-nm thick silicon-on-insulator platform designed for 4 × 800-GHz spaced wavelength-division multiplexing featuring a low average crosstalk (−30 dB), a precise channel spacing, optimized interchannel uniformity (0.7 dB) and insertion losses (3-3.5 dB) are presented. Wafer-level statistical performance analysis shows the EG spectral response to be stable over the wafer in terms of crosstalk, channel spacing, and bandwidth with minimal wavelength dispersion (<0.8 nm), thus highlighting the intrinsic robustness of high-order gratings and chosen fab pathways as well as the full reliability of 3-D vectorial modeling tools. IndexTerms-Complementary metal-oxide-semiconductor (CMOS), echelle gratings (EGs), photonic integrated circuits (PICs), silicon-on-insulator (SOI), and silicon photonics.

in this article, we report an integrated optical nanolens exhibiting a pseudo-graded index distribution in a guided configuration. This dielectric metalens relies on a permittivity distribution through dielectric strips of the core material, which is compatible with existing silicon photonic technology. We show in this paper that effective medium theory (EMT) inaccurately predicts the focal length of such devices, and we propose an efficient and accurate design approach based on 2D finite element method (FEM) mode calculations that are in good agreement with 3D FDTD simulations. The lens was fabricated on a 200 mm silicon on insulator pilot line, and fibre-to-fibre optical characterizations revealed an excellent transmission of 85% for TM polarization, in line with the simulated performance (90%). The proposed approach can be easily extended to width-variable strips, enabling the realization of all types of graded index devices, especially those derived from transformation optics.

In this communication, we report about the design, fabrication, and testing of echelle grating (de-)multiplexers for the 100GBASE-LR4 norm and other passive architectures such as vertical fiber-couplers and slow-wave waveguides in the O-band (1.31-μm) for Silicon-based photonic integrated circuits (Si-PICs). In detail, two-point stigmatic 20 th -order echelle gratings (TPSGs) on the 300-nm-thick SOI platform designed for 4x800-GHz-spaced wavelength division multiplexing featuring extremely low crosstalk (< -30 dB), precise channel spacing and optimized average insertion losses (~ 3 dB) are presented. Distributed Bragg reflectors (DBRs) are used to improve the grating facets reflectivity, while multi-mode interferometers (MMIs) are used in optimized perfectly-chirped echelle gratings (PCGs) for pass-band flattening. Moreover, 200-mm CMOS pilot lines processing tools including VISTEC variable-shape e-beam lithography are employed for the fabrication. In addition, wafer-level statistics of the multiplexers clearly shows the echelle grating to be inherently fabrication-insensitive to processing drifts, resulting in a minimized dispersion of the multiplexer performances over the wafer. In particular, the echelle grating spectral response remains stable over the wafer in terms of crosstalk, channel spacing and bandwidth, with the wavelength dispersion of the filter comb being limited to just 0.8 nm, thus highlighting the intrinsic robustness of design, fab pathways as well as the reliability of modeling tools. As well as that, apodized one-dimensional vertical fiber couplers, optimized multi-mode interferometers (MMIs) and extremely low-losses slow-light waveguides are demonstrated and discussed. The adiabatic apodization of such 1-D gratings is capable to provide band-edge group indices n g as high as 30 with propagation losses equivalent to the indexlike propagation regime.

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