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In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography to pattern the first interconnect level (metal 1).This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip (product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity of 3.8 mJ/cm 2 , providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as evidenced by electrical test results.Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

The critical role of flare in extreme ultraviolet ͑EUV͒ lithography is well known. In this work, the implementation of a robust flare metrology is discussed, and the proposed approach is qualified both in terms of precision and accuracy. The flare measurements are compared to full-chip simulations using a simplified single fractal point-spread function ͑PSF͒, and the parameters of the analytical PSF are optimized by comparing the simulation output to the experimental results. After flare map calibration, the matching of simulation and experiment in the flare range from 4 to 12% is quite good, clearly indicating an offset of about 3%. The origin of this offset is attributed to the presence of DUV light. An experimental estimate of the DUV component is found in good agreement with the predicted value.

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