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Abstract. Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has been extended to enable its use with system models in C++ and SystemC. An automotive electronics application, the integration of SystemC modules into a MATLAB/Simulink simulation by automatic wrapper generation, will show its use in the design process.

The increasing quality requirements on safety-critical electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional design constraints. This paper introduces a novel verification method based on an unified data representation of constraints to enable multi-tool verification tasks. A Constraint Engineering System is presented which provides flexible, extensible, and multi-tool definitions of complex constraints and high-order verification tasks. Existing verification and simulation tools are combined so that the achieved complexity level of the high-order verification by far exceeds the level of the single tools. The shown examples target practical applications in analog system design and demonstrate the flexibility and the potential of this new verification approach.

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