We report a high performance NPN bipolar junction transistor (BJT) processed in standard CMOS process that is applied to realize the direct conversion GSM receiver and DVB-H tuner. Through the variation of the base doping profile, performance of the NPN BJT has been tailored to meet the requirements of the RF circuits. Careful optimization is performed using both simulation and experiment. Optimized NPN BJT has maximum current gain of ~44, collector-emitter breakdown voltage of ~7V, collectorbase breakdown voltage of ~20V, Early voltage of~25V, cutoff frequency of ~8.0GHz, and maximum oscillation frequency of ~11.6GHz. Low frequency noise characteristics of the NPN BJTs are investigated and the best structure for low noise level is identified. The corner frequency of the 1/f noise is ~2kHz at a collector current of ~ 1.7mA, which is ~ 4 orders lower than that of NMOS. As the flicker noise level is much lower than the CMOS, NPN BJT is used to realize the zero intermediate frequency (ZIF) direct conversion receiver (DCR) for GSM transceiver and DVB-H tuner. The resulting GSM receiver chain has a gain of over 50dB and noise figure of 2.5~3.0dB. For DVB-H tuner operating in the range of 470~850MHz, NF of 4.5dB and IIP3 of -5dBm are achieved at a gain of 64dB Index Terms -NPN BJT, CMOS, RF, Direct Conversion, GSM, DVB-H.

No abstract

No abstract

─ Cut-off frequency (f T ) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H 21 ) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G u ) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g ds (drain conductance).Additional efforts are required to reduce g ds for continuous improvement in power gain with the scaling. V th optimization can be one of options to achieve better g ds .