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In this article, a new design of a Wilkinson power divider is presented that offers substantially improved amplitude and reduced size characteristics over a broad frequency range compared to a conventional Wilkinson power divider. The improvement in bandwidth is obtained by reducing inductance and number of lumped components in even mode. The analytical design equations for this proposed power divider are obtained using even and odd mode analysis. This power divider with a compact size is fabricated using 65 nm 1P9M CMOS technology. The measurement results show an operation bandwidth 26–40 GHz with 15 dB input, output return loss, and 0.7 dB insertion loss. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:128–131, 2017

This study entailed the development of a K-Band power amplifier (PA). The proposed PA was implemented and verified using a 65-nm bulk CMOS process. The PA was designed with two stages to obtain sufficient gain in the K band. The PA had a chip area of 0.93×0.47 mm² including RF and DC pads. The manufactured power amplifier design had a maximum saturation power of 22.4∼22.7 dBm in the 19-21 GHz frequency band, and a power added efficiency (PAE) of 39 %∼40 %. In the two-tone simulation results, the linear power and efficiency levels satisfying third-order inter-modulation distortion (IMD 3 ) below −30 dBc were confirmed to be 16∼17 dBm and 24%∼26 % in the 19∼21 GHz frequency band, respectively.