We have developed a high image quality OLED Display with motion blur reduction technology. Our latest work includes driving method which reduces motion blur using an adaptive black data insertion, brightness compensation technology, the simple structure pixel with low capacitance coupling for horizontal noise, and the multi-function integrated gate driver. The MPRT value of the OLED display panel with a fast response time was significantly affected by the frame frequency and the compensation driving method. The decrease in the MPRT value originated from the turning of the emitting pixels off in advance resulting from providing black data. The integrated gate drivers were designed to achieve the normal display, the black data insertion, and the compensation mode. The MPRT value of the 65inch UHD OLED panels was decreased to 3.4ms by using an integrated gate driver circuit. The motion blur of large-size OLED display panels was significantly reduced due to a decrease in the MPRT value.

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This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to −28.95 dB compared with 2.37 dB of the previous circuit.