Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

Seo, Jeongrim; Song, Seok-Jeong; Kim, Dowon; Nam, Hyoungsik

doi:10.1016/j.displa.2017.07.004

Cited by 7 publications

(5 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…7 indicates the comparison of normalized rising time and falling time between the conventional and proposed circuits for the 2153 rd stage. Seo et al proposed a robust gate driver circuit capable of compensating the threshold voltage shift of oxide TFTs irrespective of the enhancement and depletion modes [17]. The conventional circuit ensures the robust operation over a wide range of threshold voltage shifts, varying from −4 to +10 V. To evaluate the V OUT characteristics of the proposed circuit using the conventional circuit, similar simulation conditions are considered (RC load of CLK and V OUT , voltage level, and 1H time).…”

Section: Resultsmentioning

confidence: 99%

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Jung

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement-and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the V OUT ripple voltage because the threshold voltage (V TH) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of V TH , depletion mode: negative value of V TH). Many groups proposed the V TH compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the V TH value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the V GS value is 0 V. To solve this problem, we adopted the V TH extraction period only once in one frame time. As a result, our circuit can compensate for V TH of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and V OUT nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the V OUT waveforms are maintained at +28 V (VGH) under the V TH shift conditions from −7 V to +11 V; further, the rising time and falling time are less than 0.62 µs and 0.96 µs, respectively. Based on a 120-Hz ultra-high definition (UHD) graphics (3840×2160) display panel, the proposed circuit has uniform V OUT characteristics compared to previous V TH compensation circuit when V TH changes from −3 V to +11 V. When V TH changes from −4 V to −7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption. INDEX TERMS a-IGZO TFT, gate driver circuit, pull-down unit, enhancement mode, depletion mode, threshold voltage.

show abstract

Section: Resultsmentioning

confidence: 99%

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Jung

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…To achieve high resolution displays with narrow border, the gate driver circuits need to be integrated on the panel with the pixel array based on the TFT technology. In the recent years, a-IGZO integrated gate driver circuits have been extensively investigated and applied successfully to small and middle-sized TFT-LCDs [5][6] . Though a-IGZO TFTs show better stability compared to a-Si, several studies have demonstrated that they still show nonnegligible threshold voltage (VTH) shift with respect to bias stress and temperature [7][8] .…”

Section: Introductionmentioning

confidence: 99%

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

Zhou

Shao

et al. 2023

Symp Digest of Tech Papers

View full text Add to dashboard Cite

Recently, a‐IGZO TFTs have attracted considerable attention for ultra large‐sized and ultra high‐resolution display due to high mobility and good uniformity. The life‐time of integrated gate driver is mainly determined by the stability of low‐level maintaining and pull‐up TFTs, which always experience severe performance degradation after a long time operation. In this paper, a robust a‐IGZO integrated gate driver with dual lowlevel maintaining units is proposed and fabricated for ultra large‐sized and high resolution TFT‐LCD applications. The simulation and BTS measurement results demonstrate that proposed a‐IGZO gate driver has a large VTH shift margin, which contributes to extended life‐time of circuit operation.

show abstract

“…Moreover, it is required to supply two different negative sources, resulting in more complex signal connection with the timing controller. In addition, the gate drivers whose output module adopts AC-AC type or AC-DC type may give rise to high power consumption as well [12,13].…”

Section: Introductionmentioning

confidence: 99%

A low-power gate driver integrated by IZO-TFTs employing single negative power source

Chen

Zhou

et al. 2018

Semicond. Sci. Technol.

View full text Add to dashboard Cite

This paper proposes a new gate driver employing only a single negative power source, which is integrated by In-Zn-O TFTs with an etch stop layer (ESL) structure. A negative voltage generating module (NVGM) is developed to generate a lower voltage level than that of the negative power source, in order to completely shut down the pull-down transistors of the output module. 30 stages of the proposed gate driver are fabricated on glass substrate. It is shown that the gate driver successfully achieves full swing output signals at different clock frequencies (6.67 kHz, 66.7 kHz) and negative power sources (−4 V, −5 V, −6 V) with resistive load R L =3 kΩ and capacitive load C L =30 pF. The measured power consumption per stage of the proposed gate driver is 101 μW at the clock frequency of 66.7 kHz.

show abstract

Robust low power DC-type shift register circuit capable of compensating threshold voltage shift of oxide TFTs

Cited by 7 publications

References 10 publications

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

Novel Driving Methods of Gate Driver for Enhancement- and Depletion-Mode Oxide TFTs

P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications

A low-power gate driver integrated by IZO-TFTs employing single negative power source

Contact Info

Product

Resources

About