Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding and thinning have become key elements in device processing over the past years. While these elements are now mature enough for high-volume manufacturing, thin wafer debonding and handling still remain challenging. Hence this work focuses on a novel ZoneBOND approach to face these challenges.

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Wafer-to-wafer bonding is widely used to support both the production of integrated circuits and MEMS devices. Bonding may be accomplished in a variety of ways including anodic, thermal compression, and adhesive bonding. The bond may be either permanent or temporary. Permanent wafer bonding is used to combine two materials together that remain together for the life of the device, for example, in the production of Si/GaAs wafer heterostructures for integration of an optoelectronic device into silicon integrated circuit technology. Temporary bonding is used to support the device wafer during certain processing steps, and then removed once the device wafer is completed. Currently, there are several temporary bonding processes being developed in industry. The leading technology utilizes some form of polymeric material to temporarily fasten or bond a rigid backing material, usually silicon or glass, to the device wafer for processing. The main issues associated with these techniques are temperature stability of the adhesive, removal from the support wafer, and cleaning the adhesive from the device wafer. The ideal process would require bonding at an acceptable temperature (usually less than 200°C), surviving through higher temperature processes, followed by debonding at lower temperature or even room temperature. In this paper, an alternative solution is reported that utilizes current thermoplastic adhesives and silicon support wafers coupled with a patented technology, developed by Brewer Science, Inc. Support wafers are bonded to device wafers at acceptable temperatures, mechanical integrity is maintained through semiconductor or MEMs processing, and the completely processed device wafer is then safely debonded from the support wafer at room temperature.

A key driver for 3-D device integration has been through-silicon via (TSV) technology that enables through-chip communication between vertically integrated layers. The TSVs typically have an electrical isolation using a dielectric layer between the silicon and the interconnect metal (e.g., copper). Recently, polymers have been proposed for use as the dielectric isolation layer, and polymers have been shown to increase device reliability by reducing “copper pumping,' where copper pops out from the TSV holes during thermal cycling. Traditionally, spinor spray-coating techniques have been used to fill TSVs with polymer material. However, using those techniques to fill and planarize very deep trenches (∼ 400 μm) and high-aspect-ratio structures has many limitations and usually results in voids, nonplanar surfaces, and lack of polymer flow to the requisite depths. Here, we present a novel process and a tool to completely fill and planarize deep trenches with a polymeric material. We use a combination of a traditional spin-coating process together with a physical planarization and fill process using the contact planarization tool to evacuate the trenches or vias on the wafer and then force the polymeric material inside the features. Using this process, we successfully filled and planarized trenches and vias 180 μm deep with 50-μm wide patterns as well as 400-μm deep trenches with ∼ 400-μm wide patterns. Initial results show complete filling and planarization of the material in the trenches without any voids.