An abnormal subthreshold leakage current is observed at high temperature, which causes a notable stretch-out phenomenon in amorphous InGaZnO thin film transistors (a-IGZO TFTs). This is due to trap-induced thermal-generated holes accumulating at the source region, which leads to barrier lowering on the source side and causes an apparent subthreshold leakage current. In order to obtain superior thermal stability performance of a-IGZO TFTs, conducting N2O plasma treatment on active layer was expected to avert defects generation during SiO2 deposition process. Reducing defects generation not only suppresses subthreshold current stretch-out phenomenon but also significantly improves the bias stress stability in a-IGZO TFTs at high temperature.

This paper investigates behavior of drain bias stress and gate-drain bias stress under illumination for InGaZnO thin film transistors as the current-driver operated. Properties exhibit two-stage degradation behavior during drain bias stress. The photo-excited hole non-uniform trapping from illumination induces drain side barrier lowering and causes an apparent hump phenomenon of the subthreshold swing. However, the positive threshold voltage shift without a hump phenomenon after gate-drain bias stress is different degradation behaviors. It is reliant on whether or not an inversion layer exists in the channel. This work also employs capacitance-voltage measurement to further clarify the mechanism of degradation behaviors.

Abstract-The instability of the gate bias and drain bias stresses is observed at high temperature in amorphous InGaZnO thin-film transistors (a-IGZO TFTs). The transfer characteristics of a-IGZO TFTs at different temperatures are also investigated in this paper. The transfer curve exhibits an apparent subthreshold current stretchout phenomenon at high temperature. The stretchout phenomenon becomes more serious with the increase of the temperature. In addition, thermally induced holes are accumulated by the negative gate voltage and get trapped in the gate dielectric or at the dielectric/channel interface at high temperature. The negative threshold voltage shifts with stress time and this is because the trapped holes induce more electrons. For drain bias stress at high temperature, the transfer curve exhibits an apparent shift during drain bias stress at high temperature compared with the same at room temperature. At high temperature, thermally induced holes are trapped in the gate insulator, especially near the drain region. Capacitancevoltage measurements have been used to prove the nonuniform hole-trapping phenomenon. Furthermore, the simulation of the capacitance-voltage and current-voltage curves also have been applied to confirm the hole-trapping distribution. The obtained results clarify that the instability is caused by nonuniform hole-trapping phenomenon.Index Terms-Bias stress, indium gallium zinc oxide (IGZO), technology computer-aided design (TCAD), temperature, thin-film transistors (TFTs).

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