No abstract

An analytical expression for collector resistance of a novel vertical SiGe partially-depleted accumulation-subcollector HBT on thin SOI is obtained. Supported by simulation result, the resistance decreases quickly with the increase of substrate-collector bias and improves the transit frequency dramatically. The model is found to be significant in the design and simulation of 0.13 μm millimeter wave SiGe SOI BiCMOS technology.

The impact of Drain-Induced Barrier Lowering effect (DIBL) on the shift of threshold voltage is prominent as the feature size of MOS device continue reducing. In this paper, a threshold voltage model for small-scaled strained Si nMOSFET is proposed to illustrate the impact of DIBL effect on the threshold voltage, which is based on the distribution of the charge in depletion layer when strong inversion occurred. By simulation, the influence of DIBL to variation threshold voltage with its design physical and geometric parameters can be predicted, such as gate length, drain bias, Ge content, oxide thickness, source/drain junction depth, and doping concentration. This model is significant for the design of high performance strained Si nMOSFET to restrain the DIBL effect.