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The FPGA‐based image classification accelerator has achieved success in many practical applications. However, most accelerators focus on solving the problem of convolution computation efficiency. End‐to‐end image classification involves many non‐convolutional operations, which can also become performance bottlenecks. Therefore, the authors propose an FPGA‐based JPEG preprocessing accelerator, which can accelerate non‐convolution operations of JPEG before feature extraction. To improve throughput and energy efficiency, four hardware structures are adopted in the design: 1) adaptive image block; 2) fast IDCT; 3) image block buffer; and 4) image block self‐location. The proposed design is evaluated on Xilinx XCZU7EV. The authors compare it with the optimized implementation of CPU and GPU, and the energy efficiency is improved by 23.07 times and 4.21 times, respectively. The throughput is 2.52 times better than the CPU implementation. And the authors demonstrate its practicality through a case study of image classification. These experimental results demonstrate its superior performance in terms of throughput and energy efficiency.

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