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A CMOS down-conversion folded mixer for the radio frequency (RF) applications is presented. The proposed mixer composes of frequency doubling circuits, transconductance stages, and folded switching stages. With input 1.9GHz RF signals of -40dBm driven by 0.948GHz local oscillation (LO) signals of 0dBm, the mixer shows a good performance in both the high linearity and the low power consumption. The third-order input intercept point (IIP3) and the power consumption including the buffer stage are -3dBm and 6.4mW, respectively. The proposed mixer is designed and fabricated by tsmc 0.18μ μ μ μm 1P6M CMOS process with the size of 0.989 ͪ ͪ ͪ ͪ 0.559mm 2 .

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