Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of −5–14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

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Heterogeneous III-V/Si integration with a compact optical vertical interconnect access is fabricated and the light coupling efficiency between the III-V/Si waveguide and the silicon nanophotonic waveguide is characterized. The III-V semiconductor material is directly bonded to the silicon-on-insulator (SOI) substrate and etched to form the III-V/Si waveguide for a higher light confinement in the active region. The compact optical vertical interconnect access is formed through tapering a III-V and an SOI layer in the same direction. The measured III-V/Si waveguide has a light coupling efficiency above ~90% to the silicon photonic layer with the tapering structure. This heterogeneous and light coupling structure can provide an efficient platform for photonic systems on chip, including passive and active devices.