In this study, a mutual capacitive-type on-screen fingerprint sensor, which can recognize fingerprints on a display screen to provide smartphones with full-screen displays with a minimal bezel area, is fabricated. On-screen fingerprint sensors are fabricated using an indium tin oxide transparent conductor with a sheet resistance of ~10 Ω/sq. and a transmittance of ~94% (~86% with the substrate effect) in the visible wavelength range, and assembled onto a display panel. Even at this high transmittance, the electrodes can degrade the display quality when they are placed on the display. The interference between periodic display pixel arrays and sensor patterns can lead to the Moiré phenomenon. It is necessary to find an appropriate sensor pattern that minimizes the Moiré pattern, while maintaining the signal sensitivity. To search for appropriate patterns, a numerical calculation is carried out over wide ranges of pitches and rotation angles. The range is narrowed for an experimental evaluation, which is used to finally determine the sensor design. As the selected sensor pitches are too small to detect capacitance variations, three unit patterns are electrically connected to obtain a unit block generating a larger signal. By applying the selected sensor pattern and circuit driving by block, fingerprint sensing on a display is demonstrated with a prototype built on a commercial smartphone.

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This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18µm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast switching of power mode possible for dynamic voltage scaling and power gating. IntroductionDynamic voltage scaling (DVS) and power gating, known as effective methods to reduce power consumption of digital systems, generate large rush current at the moment when they function. This rush current causes resonant supply noise that has typically 40-200MHz frequency which is determined by the package inductance and the on-chip capacitance. The resonant noise has long duration and large magnitude, especially the 1st droop, degrades signal integrity[1]-[3]. Slow wake-up time and large on-chip decoupling capacitance (decap) are conventionally used in order to mitigate the resonant supply noise. However, slow wake-up time is not suitable for fast power mode transition, and the large decap consumes chip area. To realize fast wake-up time and low supply noise simultaneously, several noise reduction methods such as switched decap[1], active decap[2] and bypassed power line[3] are proposed.Recent SoCs have multiple power domains [4]. All function blocks of a single chip rarely work at the same time, and some blocks are sleeping. Each sleep block has plenty of parasitic capacitance. In this paper, we propose a resonant supply noise canceller utilizing the parasitic capacitance of the sleep blocks. Our canceller has small area penalty since we utilize the sleep blocks and achieves effective supply noise cancelling under the fast power mode switching for DVS and power gating systems.

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